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Altium Designer 6.7:新功能介紹 (Whats New in Altium Designer 6.7) Part.1

本主題共有 0 篇回覆,最新回覆發表於 02-25-2011, 10:21 上午,作者 tifa
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  •  02-25-2011, 10:21 上午 3887

    Altium Designer 6.7:新功能介紹 (Whats New in Altium Designer 6.7) Part.1

    Altium Designer 6.7:新功能介紹 (Whats New in Altium Designer 6.7) Part.1

    Summary
    Altium Designer 6.7 continues to improve your productivity delivering features for high-speed design
    such as Interactive Length Tuning and PCB Layer Tabs.
    New library tools and a variety of new capabilities strengthen Altium Designer
    as a unified electronic product development solution.

    You need full control over all aspects of your design in an intuitive and productive environment.
    Altium Designer 6.7 brings some noteworthy enhancements to the PCB and FPGA design process.
    A number of other areas of the software have been streamlined
    for substantial productivity improvements in areas once considered time-consuming.

    Physical platform design has been improved further to support the complex multi-layer board densities
    and high-speed signaling found in today's designs.
    A greater level of control over the routing process is accomplished with Interactive Length Tuning.
    Making sense of a visually-crowded workspace is made even easier
    with PCB Layer Tabs and a new Hole Size Editor.
    Delivering output for designs that contain embedded board arrays is improved with redesigned
    and updated output dialogs for Gerber and ODB++.

    You need to be able to fully exploit the potential offered by today's large-capacity programmable devices.
    Embedded tools support for FPGA development is expanded to allow you to take advantage of core technology
    from your favorite third party vendors with the new FPGA Third Party Core Import Wizard.

    You need better ways to manage the design process.
    It's significantly easier with this release to do design debugging in large complex pieces of code
    with new Text Editor Options and Grid Paste Tools.

    These are just a few of the new features in the release of Altium Designer 6.7.
    Read on to learn more about what's the new and improved electronic product development technology.

    New - Hole Size Editor

    An additional Hole Size Editor mode has been added to the PCB panel,
    providing a greater level of visibility and management of drill sizes on your boards.
    Various criteria can be defined to allow you to zero-in on and display only holes of interest.
    Some of these criteria allow you to consider only:

    • Holes associated with pads and/or vias.
    • Plated and/or non-plated holes.
    • Holes associated with pads/vias that are part of a component and/or free.
    • All hole types, or only round, square or slotted holes.
    • Selected and/or unselected holes.
    • Only the layer-pairs of interest.
      Once the criteria defined, the panel lists all unique hole definitions
      and subsequently the pads and/or vias associated with each.
      Click on a Unique Hole entry to view the instances of that hole in the design in accordance
      with your defined highlighting options (Zoom, Mask, and Select) for the panel.

      Figure 1. Locate and edit holes of interest quickly and efficiently in dense boards from within the PCB panel.

      Editing of a hole entry can then be carried out directly in the panel.
      Simply click in the relevant field to edit the hole's Size (ToolSize), Length, Type and whether it is to be plated or not.
      Pad or via properties can be accessed directly - double-click on an entry to access the associated properties dialog.

    Improved - PCB Layer Tabs

    Moving around a large or complex design can often mean lots of layer switching.
    You'll appreciate the fact that the PCB Layer tabs are improved to help you better manage,
    navigate and inspect layers in your design.
    Enhancements include:

    • Color-coded Layer tabs allow easier identification of layers and their content.
    • Current layer drawn name can be intuitively bolded for quicker identification.
    • Shortened layer names on tabs can give you more control over managing your space
      with less scrolling and searching for hidden layer tabs.
    • Commonly-used commands for layer-related dialogs available through right-click menu.
    • Layer visibility adjusted through right-click menu commands Show Layers and Hide Layers.
    • Conveniently accessed using the same interface as net highlighting.

      Figure 2. Layers can be highlighted through right-click menu commands as shown here,
      or through shortcut keys on the layer tabs

      (CTRL + Click highlights layer content,
      CTRL + SHIFT + Click increments highlighting, and
      CTRL + ALT + Mouse hovers highlight layer).

    New - Interactive Length Tuning

    Matching route lengths is a standard technique for maintaining data integrity in a high-speed digital system,
    and an essential ingredient of differential pair routing.

    Interactive Length Tuning allows a dynamic means of optimizing and controlling nets lengths
    by allowing variable amplitude patterns to be inserted according to the available space, rules,
    and obstacles in your design.

    Launched from the Tools menu, it can be based on design rules,
    properties of the net, or values you enter into a dialog.

    Once you have launched the command, click on the routed net
    and move the mouse along the net to add tuning segments.
    The Interactive Length Tuning cursor guides you during the tuning process.
    The yellow cursor bars indicate the possible minimum and maximum lengths.
    The green bar indicates the target length, as determined from the applicable Matched Length
    and Max Length design rules, or the settings in the Interactive Length Tuning dialog.
    The sliding indicator shows how close you are to achieving a match.
    Highlights of the Interactive Length Tuning tool include:

    • Target Length can be directed either according to rules in your design,
      a design net, or manually.
    • Three tuning styles available -Mitered with Lines, Mitered with Arcs, and Rounded.
    • Option to precisely clip tuning patterns to Target Length when Mitered with Lines
      and Mitered with Arcs styles are used.
    • Consistent interface with other Altium Designer Interactive Routing tools ensures intuitive
      and quick control using familiar keyboard shortcuts.

      Figure 3. Current length as well as valid length range is displayed dynamically using the gauge bar.
      Hitting the TAB key (or press SHIFT + F1 for shortcut keys)
      while you are routing will bring up the new Interactive Length Tuning dialog
      where you can make changes as needed.

    Improved - Polygon Placement and Editing

    Placement of polygon outlines now follows a similar behavior that you are accustomed to in interactive routing -
    being more intuitive and allowing greater control and flexibility.
    Additionally, editing of placed polygons supports the sliding of edges (including arcs).

    Figure 4. Greater control when placing and editing polygons: note that the Sliding of polygon edges
    can only be performed when in Move Polygon Vertices mode (Edit » Move » Polygon Vertices).

    Improved - Smart Drag now Supports Arcs

    The Smart Drag functionality has been extended to support arcs, allowing for quick
    and efficient manipulation of arc-mitered corners.

    Figure 5. Simply click to select the routing segment(s) you wish to drag -
    the cursor will change to a quad arrow -
    and then click and drag to slide to the new location. Alternatively,
    use the CTRL + Click & drag shortcut to drag without having to select first.

    New and Improved - Embedded Board Array

    The Gerber and ODB++ Setup dialogs have been redesigned and updated making it easier to create
    and deliver output for designs that contain embedded board arrays.
    Added intelligence identifies any layer stackup violations before you output,
    and gives you an option to either continue with output or review a new Stackup Compatibility report.

    With your embedded board array project open in the PCB Editor, select File » Fabrication Outputs.
    Select the output format you require and your design is analyzed automatically for layer stackup violations.
    Enhancements in the Gerber and ODB++ Setup dialogs include:

    • Ability to preview Gerber files extensions for each layer and ODB++ directory structure.
    • Embedded boards that are flipped will display their layer stacks as flipped.
    • Mid signal layers and internal planes that are different can still appear on the same mid layer panel.
    • Mid signal layers and internal planes can be flipped against each other.

      Figure 6.The new Gerber and ODB++ Setup dialogs display layer stackups for embedded board arrays.
      Notice here that any compatibility violations display in red.


      Figure 7. When generating output, a warning dialog alerts you if the layer stacks are incompatible.
      You then have the option of deciding to go forward with output or resolving the violation.

      The new Stackup Compatibility report features:
    • Immediate feedback on the layer stackup of any embedded board arrays in the current Fabrication panel.
    • Hyperlinks for the Layer Stack Manager allow access for resolving violations quickly.
    • Report can be viewed either at the time of output generation or run from the Reports menu in the PCB Editor.

      Figure 8. The Stackup Compatibility report shows incompatible layers in red a
      nd the total count of violations at the top of the report.

    New - FPGA Third Party Core Import Wizard

    Embedded tools support for FPGA development is expanded to allow you to take advantage of core technology
    from your favorite third party vendors -
    providing increased linking of vendor-specific FPGA cores with the designs that incorporate them.

    Available through the Tools menu when a schematic document in an FPGA project is active,
    the new wizard automates importing third party IP cores from FPGA vendor tools
    such as Xilinx, Altera, Actel, and Lattice.

    Some features of the FPGA Third Party Core Import Wizard include:

    • Schematic components and their corresponding libraries are automatically created
      with the correct parameters (ChildModel parameters) ready to use.
    • Sheet symbols are created for HDL formats such as Altera's Megafunction Core Wizard.
    • Binary file formats, such as NGC, are supported.
    • Ability to declare and instantiate a core in a VHDL or Verilog file is supported.
    • Non-design files such as memory initialization can be associated as part of the core.

      Figure 9. Multiple IP files are supported. For better management,
      there are options for copying to a project directory or zipping up core files together.

    New - IPC® Compliant Footprints Batch Generator

    Available through the Tools menu when a PCB library is the active document,
    the IPC® Compliant Footprint Batch Generator makes it possible to quickly generate multiple footprints
    as well as multiple density levels for a single component from a package input file
    that contains datasheet package information.

    Figure 10. The IPC® Compliant Footprint Batch Generator has options
    that either create all the footprints into the current open .PcbLib, or generate a single .

    PcbLib file based on either an input file or footprint name.
    Support for the IPC Compliant Footprints Batch Generator includes:

    • Package type blank template files can be opened within the dialog
      and are provided in the \Templates folder of the installation directory.
      Help for any of the package type templates is also available.
    • Package input files need only to contain the information for one or more footprints of a single package type,
      and can be either an Excel or comma-delimited file format.

    相關文章:
    Altium Designer 6.6:新功能介紹 (Whats New in Altium Designer 6.6) Part.1
    http://bbs.stella.com.tw/forums/thread/3882.aspx
    Altium Designer 6.6:新功能介紹 (Whats New in Altium Designer 6.6) Part.2
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    Altium Designer 6.0:新功能介紹 (Whats New in Altium Designer 6.0) Part.4
    http://bbs.stella.com.tw/forums/thread/3873.aspx

    New - Hole Size Editor

    An additional Hole Size Editor mode has been added to the PCB panel,
    providing a greater level of visibility and management of drill sizes on your boards.
    Various criteria can be defined to allow you to zero-in on and display only holes of interest.
    Some of these criteria allow you to consider only:

    • Holes associated with pads and/or vias.
    • Plated and/or non-plated holes.
    • Holes associated with pads/vias that are part of a component and/or free.
    • All hole types, or only round, square or slotted holes.
    • Selected and/or unselected holes.
    • Only the layer-pairs of interest.
      Once the criteria defined, the panel lists all unique hole definitions
      and subsequently the pads and/or vias associated with each.
      Click on a Unique Hole entry to view the instances of that hole in the design in accordance
      with your defined highlighting options (Zoom, Mask, and Select) for the panel.

      Figure 1. Locate and edit holes of interest quickly and efficiently in dense boards from within the PCB panel.

      Editing of a hole entry can then be carried out directly in the panel.
      Simply click in the relevant field to edit the hole's Size (ToolSize), Length, Type and whether it is to be plated or not.
      Pad or via properties can be accessed directly - double-click on an entry to access the associated properties dialog.

    Improved - PCB Layer Tabs

    Moving around a large or complex design can often mean lots of layer switching.
    You'll appreciate the fact that the PCB Layer tabs are improved to help you better manage,
    navigate and inspect layers in your design.
    Enhancements include:

    • Color-coded Layer tabs allow easier identification of layers and their content.
    • Current layer drawn name can be intuitively bolded for quicker identification.
    • Shortened layer names on tabs can give you more control over managing your space
      with less scrolling and searching for hidden layer tabs.
    • Commonly-used commands for layer-related dialogs available through right-click menu.
    • Layer visibility adjusted through right-click menu commands Show Layers and Hide Layers.
    • Conveniently accessed using the same interface as net highlighting.

      Figure 2. Layers can be highlighted through right-click menu commands as shown here,
      or through shortcut keys on the layer tabs

      (CTRL + Click highlights layer content,
      CTRL + SHIFT + Click increments highlighting, and
      CTRL + ALT + Mouse hovers highlight layer).

    New - Interactive Length Tuning

    Matching route lengths is a standard technique for maintaining data integrity in a high-speed digital system,
    and an essential ingredient of differential pair routing.

    Interactive Length Tuning allows a dynamic means of optimizing and controlling nets lengths
    by allowing variable amplitude patterns to be inserted according to the available space, rules,
    and obstacles in your design.

    Launched from the Tools menu, it can be based on design rules,
    properties of the net, or values you enter into a dialog.

    Once you have launched the command, click on the routed net
    and move the mouse along the net to add tuning segments.
    The Interactive Length Tuning cursor guides you during the tuning process.
    The yellow cursor bars indicate the possible minimum and maximum lengths.
    The green bar indicates the target length, as determined from the applicable Matched Length
    and Max Length design rules, or the settings in the Interactive Length Tuning dialog.
    The sliding indicator shows how close you are to achieving a match.
    Highlights of the Interactive Length Tuning tool include:

    • Target Length can be directed either according to rules in your design,
      a design net, or manually.
    • Three tuning styles available -Mitered with Lines, Mitered with Arcs, and Rounded.
    • Option to precisely clip tuning patterns to Target Length when Mitered with Lines
      and Mitered with Arcs styles are used.
    • Consistent interface with other Altium Designer Interactive Routing tools ensures intuitive
      and quick control using familiar keyboard shortcuts.

      Figure 3. Current length as well as valid length range is displayed dynamically using the gauge bar.
      Hitting the TAB key (or press SHIFT + F1 for shortcut keys)
      while you are routing will bring up the new Interactive Length Tuning dialog
      where you can make changes as needed.

    Improved - Polygon Placement and Editing

    Placement of polygon outlines now follows a similar behavior that you are accustomed to in interactive routing -
    being more intuitive and allowing greater control and flexibility.
    Additionally, editing of placed polygons supports the sliding of edges (including arcs).

    Figure 4. Greater control when placing and editing polygons: note that the Sliding of polygon edges
    can only be performed when in Move Polygon Vertices mode (Edit » Move » Polygon Vertices).

    Improved - Smart Drag now Supports Arcs

    The Smart Drag functionality has been extended to support arcs, allowing for quick
    and efficient manipulation of arc-mitered corners.

    Figure 5. Simply click to select the routing segment(s) you wish to drag -
    the cursor will change to a quad arrow -
    and then click and drag to slide to the new location. Alternatively,
    use the CTRL + Click & drag shortcut to drag without having to select first.

    New and Improved - Embedded Board Array

    The Gerber and ODB++ Setup dialogs have been redesigned and updated making it easier to create
    and deliver output for designs that contain embedded board arrays.
    Added intelligence identifies any layer stackup violations before you output,
    and gives you an option to either continue with output or review a new Stackup Compatibility report.

    With your embedded board array project open in the PCB Editor, select File » Fabrication Outputs.
    Select the output format you require and your design is analyzed automatically for layer stackup violations.
    Enhancements in the Gerber and ODB++ Setup dialogs include:

    • Ability to preview Gerber files extensions for each layer and ODB++ directory structure.
    • Embedded boards that are flipped will display their layer stacks as flipped.
    • Mid signal layers and internal planes that are different can still appear on the same mid layer panel.
    • Mid signal layers and internal planes can be flipped against each other.

      Figure 6.The new Gerber and ODB++ Setup dialogs display layer stackups for embedded board arrays.
      Notice here that any compatibility violations display in red.


      Figure 7. When generating output, a warning dialog alerts you if the layer stacks are incompatible.
      You then have the option of deciding to go forward with output or resolving the violation.

      The new Stackup Compatibility report features:
    • Immediate feedback on the layer stackup of any embedded board arrays in the current Fabrication panel.
    • Hyperlinks for the Layer Stack Manager allow access for resolving violations quickly.
    • Report can be viewed either at the time of output generation or run from the Reports menu in the PCB Editor.

      Figure 8. The Stackup Compatibility report shows incompatible layers in red a
      nd the total count of violations at the top of the report.

    New - FPGA Third Party Core Import Wizard

    Embedded tools support for FPGA development is expanded to allow you to take advantage of core technology
    from your favorite third party vendors -
    providing increased linking of vendor-specific FPGA cores with the designs that incorporate them.

    Available through the Tools menu when a schematic document in an FPGA project is active,
    the new wizard automates importing third party IP cores from FPGA vendor tools
    such as Xilinx, Altera, Actel, and Lattice.

    Some features of the FPGA Third Party Core Import Wizard include:

    • Schematic components and their corresponding libraries are automatically created
      with the correct parameters (ChildModel parameters) ready to use.
    • Sheet symbols are created for HDL formats such as Altera's Megafunction Core Wizard.
    • Binary file formats, such as NGC, are supported.
    • Ability to declare and instantiate a core in a VHDL or Verilog file is supported.
    • Non-design files such as memory initialization can be associated as part of the core.

      Figure 9. Multiple IP files are supported. For better management,
      there are options for copying to a project directory or zipping up core files together.

    New - IPC® Compliant Footprints Batch Generator

    Available through the Tools menu when a PCB library is the active document,
    the IPC® Compliant Footprint Batch Generator makes it possible to quickly generate multiple footprints
    as well as multiple density levels for a single component from a package input file
    that contains datasheet package information.

    Figure 10. The IPC® Compliant Footprint Batch Generator has options
    that either create all the footprints into the current open .PcbLib, or generate a single .

    PcbLib file based on either an input file or footprint name.
    Support for the IPC Compliant Footprints Batch Generator includes:

    • Package type blank template files can be opened within the dialog
      and are provided in the \Templates folder of the installation directory.
      Help for any of the package type templates is also available.
    • Package input files need only to contain the information for one or more footprints of a single package type,
      and can be either an Excel or comma-delimited file format.

    相關文章:
    Altium Designer 6.6:新功能介紹 (Whats New in Altium Designer 6.6) Part.1
    http://bbs.stella.com.tw/forums/thread/3882.aspx
    Altium Designer 6.6:新功能介紹 (Whats New in Altium Designer 6.6) Part.2
    http://bbs.stella.com.tw/forums/thread/3883.aspx
    Altium Designer 6.3
    :新功能介紹 (Whats New in Altium Designer 6.3) Part.1
    http://bbs.stella.com.tw/forums/thread/3875.aspx
    Altium Designer 6.3:新功能介紹 (Whats New in Altium Designer 6.3) Part.2 
    http://bbs.stella.com.tw/forums/thread/3876.aspx
    Altium Designer 6.0:新功能介紹 (Whats New in Altium Designer 6.0) Part.1
    http://bbs.stella.com.tw/forums/thread/3869.aspx
    Altium Designer 6.0:新功能介紹 (Whats New in Altium Designer 6.0) Part.2
    http://bbs.stella.com.tw/forums/thread/3871.aspx
    Altium Designer 6.0:新功能介紹 (Whats New in Altium Designer 6.0) Part.3
    http://bbs.stella.com.tw/forums/thread/3872.aspx
    Altium Designer 6.0:新功能介紹 (Whats New in Altium Designer 6.0) Part.4
    http://bbs.stella.com.tw/forums/thread/3873.aspx

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