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Altium Designer 6.0:新功能介紹 (Whats New in Altium Designer 6.0) Part.2

本主題共有 0 篇回覆,最新回覆發表於 02-22-2011, 11:43 上午,作者 tifa
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  •  02-22-2011, 11:43 上午 3871

    Altium Designer 6.0:新功能介紹 (Whats New in Altium Designer 6.0) Part.2

    Altium Designer 6.0:新功能介紹 (Whats New in Altium Designer 6.0) Part.2

    Build Bigger, Better Boards

    Designing with Differential Pairs

    Differential signaling is fast becoming the preferred signaling interface method,
    driven by the ever increasing signal speeds in electronic products.
    By their very nature FPGAs are ideally suited to high-speed designs,
    and in support of this FPGA vendors are including differential signaling capabilities (LVDS),
    from their lower-cost devices right through to their high-end 1500+ pin mega-gate devices.

    Altium Designer 6.0 has excellent support for differential signaling -
    from defining pairs on the schematic, through to interactive differential pair routing on the PCB.
    PCB routing is backed up by full support for pair swapping
    using Altium Designer's new dynamic net assignment capabilities,
    an exciting concept that can swap not only unrouted net pairs, but also partially routed net pairs,
    allowing you to harness the full benefits of the FPGA's reconfigurable design capabilities
    throughout the routing process.

    Background

    A differential signaling system is one where a signal is transmitted down a pair of tightly coupled carriers,
    one of these carrying the signal, the other carrying an equal but opposite image of the signal.
    Differential signaling was developed to cater for situations where the logic reference ground of the signal source
    could not be well connected to the logic reference ground of the load.
    Differential signaling is inherently immune to common mode electrical noise,
    the most common interference artifact present in an electronic product.
    Another major advantage of differential signaling is
    that it minimizes electromagnetic interference (EMI) generated from the signal pair.

    Differential pair routing is a design technique employed to create a balanced transmission system
    able to carry differential (equal and opposite) signals across a printed circuit board.
    Typically this differential routing will interface to an external differential transmission system,
    such as a connector and cable.

    It is important to note that while the coupling ratio achieved in a twisted pair differential cable
    may be better than 99%, the coupling achieved in differential pair routing will typically be less than 50%.
    Current expert opinion is that the PCB routing task is not to try to ensure a specific differential impedance is achieved,
    rather the objective is to maintain the properties required to ensure the differential signal arrives
    in good condition at the target component as it travels from the external cabling.

    According to Lee Ritchey, a noted industry high-speed PCB design expert,
    successful differential signaling does not require working to a specific differential impedance.
    What it does require is:

    • To set each of the routing signal impedances to half the incoming differential cable impedance.
    • That each of the two signal lines is properly terminated in its own characteristic impedance at the receiver end.
    • That the two lines should be of equal length, to within tolerances of the logic family.
      Typically a length difference of up to 500mils is acceptable.
    • Use the benefit of routing the two signals side-by-side to help achieve good quality routing of matched lengths,
      where required it is acceptable to separate to route around obstacles.
    • Layer changes are acceptable, as long as the signal impedances are maintained.
      For more information, refer to the article Differential Signaling Doesn't Require Differential Impedance,
      by Lee W. Ritchey, available from http://www.speedingedge.com/RelatedArticles.htm.


    Defining the Differential Pairs on the Schematic

    Pairs can be defined on the schematic by placing a Differential Pair directive (Place » Directive).
    The net pair must be named with the suffixes of _N and _P. Differential pair definitions
    are then transferred to the PCB during design synchronization.


    Figure 18. Place Directives on the schematic to define differential pairs.


    Defining the Differential Pairs on the PCB


    Figure 19. Differential pairs can be viewed and managed in the Differential Pair Editor.

    For those special circumstances where pairs cannot be defined on the schematic,
    differential Pair objects can also be defined in the PCB editor.
    To create a Differential Pair object in the PCB editor and assign two nets to it
    you can either select the two nets in the graphical space using the Place » Differential Pair command,
    or click the Create From Nets button in the PCB editor panel, set to the new Differential Pair Editor mode.


    Viewing and Managing the Pairs

    Differential pair definitions are viewed and managed in the PCB editor panel,
    set to Differential Pairs Editor.
    Figure 19 shows the pairs that belong to the All Differential Pairs class.
    Pair D_V_TX1 is highlighted, the nets in this pair are V_TX1N and V_TX1P.
    The and displayed next to each member net name is a system flag,
    indicating if it is the positive or negative member of the pair.


    Applicable Design Rules

    There are three design rules you will need to configure to route a differential pair.
    These are:

    • Routing Width - defines the routing width required for both nets in the pair.
      Set the scope of this rule to target objects that are members of a differential pair, eg.
      InDifferentialPair .
    • Differential Pairs Routing - defines the separation between the nets in the pair, the gap allowed,
      and the overall uncoupled length (the pair is uncoupled when the gap is wider than the Max Gap setting).
      |Set the scope of this rule to target objects that are a differential pair, eg.
      IsDifferentialPair .
    • Match Net Length - define how much the overall routing lengths can differ for the two nets in the pair.
      Note that the rule is also used to configure the routing shape to be used
      if you run the Equalize Net Length command.
      Set the scope of this rule to target objects that are a differential pair, eg.
      IsDifferentialPair .


    Setting the Scope of the Design Rules

    The scope of the design rule defines the set of objects that you want the rule to applied to.
    Since a differential pair is an object,
    you can use queries like the following examples to scope the rule to target differential pairs:

    • InDifferentialPairClass('All Differential Pairs') -
      targets all nets in all pairs belonging to the differential pair class called All Differential Pairs.
    • InDifferentialPair('D_V_TX1') -
      targets both nets in the differential pair named D_V_TX1.
    • InAnyDifferentialPair -
      targets any object that is in a differential pair.
    • (IsDifferentialPair And (Name Like 'D'))* -
      targets all differential pair objects whose name starts with the letter D.


    Using the Differential Pair Wizard to Define the Rules


    Figure 20. The differential pair rule wizard

    Clicking the Rule Wizard button in the Differential Pairs Editor (PCB panel)
    will walk you through the process of setting the required design rules.

    Note that the scope used for the created rules will depend on what was selected
    when the Rule Wizard button was clicked -
    if one pair was selected the rules will target that pair and its nets,
    but if a differential pair class was selected then the rules will target all the nets and pairs in that class.


    Routing a Differential Pair

    Differential pairs are routed as a pair - that is you route two nets simultaneously.
    To route a differential pair select Place » Differential Pair Routing from the menus.
    You will be prompted to select one of the nets in the pair, click on either to start routing.

    Figure 21 shows a differential pair being routed.
    To make the connection lines for the pair easier to see, click on the pair in the Differential Pair Editor.
    This will mask all other nets in the design.

    Figure 21. Both nets in the differential pair are routed simultaneously, press
    ~ (tilde) to see the shortcuts.

    Differential pairs are routed using Altium Designer's new Smart Interactive Routing mode,
    which is described earlier in this document.

    Standard routing shortcuts remain, such as pressing the ***
    key on the numeric keypad to switch to the next routing layer.
    For a list of all shortcuts available during differential pair routing, press the ~ (tilde) key.


    Full Differential Pair Support for FPGA Designs, Including Pin-pair Swapping

    Modern FPGAs, even those with very low cost,
    have a large number of I/O pins that can be configured as differential pairs.
    To make it easy to harness the power of these Altium Designer 6.0
    includes full support for integration of FPGA-based differential pairs,
    in both the FPGA design and the PCB design.

    In your FPGA design you can assign a single net to a differential I/O standard,
    such as LVDS, and this will be mapped to a pair of physical nets at the PCB design level.
    This process is under your control using the FPGA Signal Manager.
    The design compiler can also determine if the pins used as differential pairs at the PCB design level map
    correctly to the allowable pairs on an FPGA device.

    Figure 22. Differential support flows from FPGA design through to PCB design.


    Signal Integrity Support for Differential Pairs

    Altium Designer's Signal Integrity analyzer provides full support for the simulation of differential pairs.
    This uses the correct signal integrity model for pins when using the LVDS standard with FPGAs.


    Pin / Part Swapping with Dynamic Net Assignment

    Working in harmony with the new differential pair routing and BGA escape routing capabilities
    is the new pin swapping capabilities.
    This feature provides all the benefits of traditional pin-swapping systems,
    but takes advantage of Altium Designer's intimate understanding of the net assignments in the design
    to lift pin swapping to a new level.

    During a pin swap operation Altium designer analyses the net assigned to the chosen pin,
    and dynamically reassigns the net on any connected routing.


    Figure 23. The 2-stage automatic pin/net optimizer minimizes connection length and crossovers.

    This level of functionality means that partially routed nets and pre-routed multilayer escapes
    from complex BGA devices can now be swapped.
    Differential pairs can now also be swapped,
    taking advantage of the knowledge about differential pin-pairs on FPGAs.

    At the PCB level the system includes a powerful automatic optimizer
    that uses this information to dynamically re-assign nets to improve routability.
    For example, the system can perform a reconnect on multiple devices
    that have been escape routed on multiple layers.
    It will assign these based on matching escape route layers,
    shortest Manhattan routing distance, and minimum number of crossovers on each layer.

    The addition of partial routed net swapping, along with the automatic optimizer gives you the ability
    to adopt a hierarchical and iterative routing strategy, escape routing devices first,
    then routing to the edge of a given area, and then finally connecting these sections together.
    At any time, the automatic swapper can be re-run to re-optimize,
    based on the updated information provided by the partially routed nets.


    Configuring Pin and Part Swapping

    Pin and part swap-ability settings are stored in the schematic component,
    while the option to allow pin or part swapping on a specific component is enabled in the PCB editor,
    and stored in the PCB component.

    Pin swap settings can be configured in the schematic and schematic library editors,
    or the PCB editor, look for a Configure Pin Swapping command in the Tools menu of each editor.

    Selecting this will open the Swap Manager, Figure 24 shows the PCB editor Swap Manager.
    The Swap Manager lists all components used in the design (or library), with their current swap settings.
    The PCB editor Swap Manager includes additional columns for enabling/disabling swapping
    on each component on the board.
    The Swap Manager includes a powerful right-click menu,
    making it very easy to quickly copy the settings from one component to another,
    or enable/disable multiple components in a single click.

    Figure 24. Use the Swap Manager to configure and manage pin swapping for all components in the design.


    Double-clicking on a component will open the Configure Pin Swapping dialog,
    as shown in Figure 25 and Figure 26. Here you can set up both the pin and part swapping specifications for that device.


    Figure 25. Configure the pin and part swapping for an individual component, in this case an FPGA.

    The basic rule of swap-ability is that if they share the same swap value, then they can be swapped.
    Consider the simple examples shown below, the pin swapping configuration for a quad OR gate,
    and a quad op-amp.

    Pin/part swap settings for a quad OR gate

    Pin/part swap settings for a quad op-amp


    Figure 26. Use alpha and numerical swap values to define swap-ability.

    From the previous figure the following can be observed:

    • Within each of the 4 gates in the quad OR gate,
      the 2 input pins can be swapped with each other,
      but the output pin has no pin with a matching swap value within that part.
      On the other hand, the quad op-amp has no swappable pins.
    • The Part Group column defines the swap-ability of the part that that pin belongs to.
      Note that it does not define which part the pin belongs to,
      that is defined by the way the component was created in the schematic library.
      All 4 parts in both quad devices are swappable with any other part in that device.
    • Pins with no Pin Group swap value are not swappable, as shown for the quad op-amp.
    • Pins with no Part Group swap value means that the part they belong to is not swappable.
    • The Part-Sequence defines the pin correspondence between parts.
      This information is required so that the part swapper knows
      how to re-allocate the nets to each pin in the part when a swap is performed.
      Note that for the quad OR gate either input pin can map to either input pin when a part swap occurs.
      Note that for the quad op-amp the net on a negative input pin must go to
      another negative input pin when a part swap occurs.


    Swapping Pins and Parts

    Pin/part swapping is enabled/disabled for a component once it is placed on the PCB.
    You can enable it selectively for any component in the PCB Inspector panel
    (click once on the component to select it, then press F11 to display the Inspector).
    Alternatively, you can enable pin and/or part swapping for any component on the board in the Swap Manager,
    as shown in Figure 24. Use the right-click menu in this dialog to quickly set the swap options for multiple components.
    Once pin/part swapping has been enabled,
    use the commands in the PCB editor's Tools » Pin/Part Swapping sub-menu to perform a pin or part swap.

    The process is essentially the same for both pin and part swapping,
    after selecting the command everything in the PCB workspace is masked (faded),
    except those pins that are swappable.

    The Status line will prompt you for the next action, to choose a sub-net (for a pin swap)
    or sub-part (for a part swap). After clicking on a pin,
    you will be prompted to select the target net or sub-part to swap with.

    Figure 27 shows this for a quad resistor array, for a pin-swap the target net is the resistor's other pin,
    for a part-swap the target sub-part is one of the other 3 resistors in the array.

    Figure 27. Swappable pins are highlighted (first image).
    After clicking the first pin during a pin swap, possible target pins are highlighted (centre image. )
    After clicking a pin in the part during a part swap, the target parts are highlighted (last image).


    BGA Escape Routing


    Figure 28. Note how the escape route feature presents each connected pad
    as an accessible route outside the edge of the BGA.

    Altium Designer has excellent surface mount component fanout tools.
    These have been enhanced by the addition of support for BGA Escape routing.
    The escape routing engine will attempt to route each pad out to just beyond the edge of the device -
    making the remaining routing challenge much easier.

    Figure 28 shows the escape routing from a 1mm pad pitch BGA.
    Used inner pads are first fanned out using the traditional dog-bone (a short route with a via on the end)
    to access another layer, and then from the via they are escape routed out just beyond the edge of the device,
    working through the available routing layers until all pads have been escape routed.

    Right-click on a BGA and select Component Actions » Fanout Component from the context menu.
    The routing will be done in accordance with the applicable design rules.
    A report of all pads that could not be escape routed will be generated and opened,
    click on an entry in the report to cross probe to the PCB and examine that object.

    TrueType Font Support


    Figure 29. Use the new TrueType font support to display text
    in your preferred font face.

    The PCB editor now has full support for TrueType® fonts.
    This gives you access to all the TrueType fonts available on your PC,
    including Unicode-character sets, such as Japanese.
    Place your company or product name in your preferred font and give your board the high-quality look it deserves.
    All PCB text strings can be set to one of the PCB editor's 3 built-in fonts,
    or to a TrueType font available on the PC.
    As well as Bold and Italic, TrueType strings can also be inverted, ideal when you need a string in the copper.

    Fonts can be embedded in the PCB file by enabling the Embed TrueType fonts option in the Preferences dialog.
    If a TrueType font is not embedded and the font is not available when the file is reopened on a different PC,
    the specified alternate system font will be used in its place.

    TrueType characters are rendered as region objects when Gerber or ODB++ output is generated,
    giving full support through to board fabrication.


    Improved Interactive Routing

    One of the most focused and intense phases of board design is routing.
    Altium Designer is known for its excellent interactive routing capabilities,
    intuitively giving you the right track width on that layer,
    easing the path finding process with the look-ahead feature,
    and instantly removing any redundant track segments
    when you re-route a section as you explore possible route path options.

    Interactive routing draws its information from the design rules,
    when you select Interactive Routing and click on a pad to start routing the rules system
    supplies the correct track width to use on that layer,
    and ensures that the required clearances are maintained.

    While this fulfills your routing needs most of the time,
    as a designer you know that there are times when you need finer control over the routing process.


    Figure 30. Select from the list of favorite routing widths by pressing SHIFT
    + W during routing. |

    Altium Designer 6.0 brings a new level of control to interactive routing.
    While still giving you the confidence and security of the boundaries defined by the design rules,
    there are new options that give added flexibility in operating within them.
    To change the width during interactive routing you can:

    1. Pick from a list of favorite widths while you route,
      press SHIFT + W to display the Choose Routing Width list, click a new value,
      and continue routing.
      Edit the entries in the list via the Interactive Routing page of the Preferences dialog.
    2. Alternatively, define your preferred widths for a net in the Edit Net dialog.
      Right-click on any object in a net,
      and choose Properties from the Net Actions sub menu to open the Edit Net dialog.
      Or double click on the net name in the PCB panel to open the dialog.
      These user-choice values are stored with the net.
    3. For the ultimate level of control, you can enter a specific width while you are routing.
      Using Altium Designer's generic edit on-the-fly feature that is available during schematic or
      PCB object placement, pressing TAB will open the Interactive Routing for Net dialog,
      simply type in the new value and press ENTER to apply the value to the connection being routed.
      You still have the full protection of the rules system,
      if the number you choose is outside the min-max rule setting then the width
      you get will be clipped back to the minimum or maximum, whichever is appropriate.
      An intuitive extension to the interactive router's behavior is its ability to pick up the width from existing routes.
      When you start routing this feature will automatically assign the new route the same width as the existing routing.
      To temporarily inhibit the pickup behavior hold the SHIFT key as you start to route.
      Or to pickup a width from some other existing track under the cursor, press the INSERT key.
      Current layer objects have higher priority.

      Interactive routing options are configured in the PCB Editor -
      Interactive Routing page of the Preferences dialog.

    Figure 31. Edit the net attributes, including the current interactive routing settings, in the Edit Net dialog.


    Preserve Track Angles While Dragging

    During board design you will often want to move existing routing.
    This process has been greatly simplified in Altium Designer 6.0.
    When you drag a track segment the angle to adjoining track segments is preserved, maintaining the routing quality.

    This capability is enabled by turning on the Preserve Angle
    When Dragging option in the PCB General page of the Preferences dialog.
    A track segment is dragged (remains attached to the segments at either end) if it is selected before you Click
    + Drag. You can also use the new CTRL + Click
    + Drag shortcuts to drag without first selecting.
    With this option enabled you can also create new segments by dragging the end handle on a track segment -
    a new track segment is added, maintaining the horizontal/45/vertical behavior.
    To inhibit the add-segment behavior,
    hold the ALT key before performing the drag operation.
    The new dragging method obeys the Ignore Obstacle and Avoid Obstacle routing modes
    (use the SHIFT + R shortcuts to cycle through the modes).

    Figure 32. Preserve angles as you drag a track segment.


    相關文章:
    Altium Designer 6.0
    新功能介紹 (Whats New in Altium Designer 6.0) Part.1
    http://bbs.stella.com.tw/forums/thread/3869.aspx

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