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Altium Designer 6.8:新功能介紹 (Whats New in Altium Designer 6.8) Part.4

本主題共有 0 篇回覆,最新回覆發表於 03-01-2011, 10:57 上午,作者 tifa
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  •  03-01-2011, 10:57 上午 3896

    Altium Designer 6.8:新功能介紹 (Whats New in Altium Designer 6.8) Part.4

    Altium Designer 6.8:新功能介紹 (Whats New in Altium Designer 6.8) Part.4

     

    New - DxDesigner* ® Importer

    Translating complete DxDesigner designs,
    including schematics and library files can all be directly imported by having Altium Designer's Import Wizard
    without having to convert to an intermediary format
    - thus avoiding the need for having DxDesigner installed.
    Such files will be converted into Altium Designer schematic documents (.SchDoc)
    - one schematic document per sheet defined within the Logic file
    - and added to a PCB project (
    .PrjPcb).

    The Import Wizard (File » Import Wizard) removes much of the headache normally found with design translation
    by analyzing your files and offering many defaults and suggested settings such as project folders,
    project links to other libraries, drawing styles, and output project structure.
    Complete flexibility is found in all pages of the wizard, giving you as little or as much control
    as you would like over the translation settings before committing to the actual translation process.

    The following versions of DxDesigner files are supported: 2004 and 2005.
    To get started with this Importer, refer to a new application note
    [Moving to Altium Designer from Mentor Graphics DxDesigner]

    New - OpenBus System

    Until now, processor-based FPGA design has been performed with all devices
    in the system layed out on a single schematic sheet.
    Such designs are inherently complex in terms of readability and,
    more importantly, from a wiring and configuration perspective.

    Altium Designer 6.8 introduces new OpenBus System feature to reduce such design complexity.
    Processor-peripheral interconnections are represented in a more abstract way
    by providing a design environment for creating your system that is highly intuitive, streamlined, and less prone to error.
    OpenBus System focuses primarily on the representation of the main processor system within an FPGA design.


    Figure 32. Graphically build your processor-based system using the OpenBus Editor.

    Familiar Schematic-like Editing Environment

    OpenBus System is created and managed using Altium Designer's OpenBus Editor .
    The OpenBus Editor has the familiar look and feel of Altium Designer's Schematic Editor,
    with it's own unique set of resources for creation of an OpenBus System.
    Filtering and inspection are provided courtesy of OpenBus Filter, OpenBus Inspector
    and OpenBus List panels, accessed from the OpenBus panel access button,
    to the bottom-right of the main design window. T
    hese resources provide a raised abstraction level for creating your processor-based design
    in a more visual and intuitive way.

    To add a new OpenBus System document type to your design, simply right-click on the name of the FPGA project
    in the Projects panel and choose Add New to Project » OpenBus System Document from the context-sensitive menu.
    Any FPGA design project that uses this system must have a top-level schematic
    as all interface circuitry remains on the top-sheet.
    The main processor system is defined in a separate, OpenBus System document (*.OpenBus).

    Connectivity between the two is made through a sheet symbol placed on the schematic.
    The starting point for any OpenBus System document is the placement of the required devices
    that will consitute your system. In the OpenBus Editor, the corresponding OpenBus components
    are placed from the OpenBus Palette panel. Placement of components is a simple two-click affair
    - once on the required entry in the panel, and once in the workspace at the desired location.

    Placement of the constituent system building blocks is simple, and wiring up the system is equally easy.
    In the OpenBus System, the individual bus interface signals are not exposed,
    only a single port represents an interface.
    Two components are connected to each other using a single link, referred to as an OpenBus Link.
    Links are made between ports of devices, with direction always
    being from a master port (red) to a slave port (green).

    The OpenBus Editor provides numerous commands for reshaping links post-placement,
    allowing you to craft the graphical depiction of your system exactly the way you want it.

    System Configuration


    OpenBus System is designed to facilitate the creation of a processor-based system
    as quickly and as intuitively as possible.
    Configuring your system to ensure correct decoding widths, port data widths and addressing is equally easy.
    Some schematic components are configurable, for example processors, certain peripherals,
    memory controllers and interconnects.
    Corresponding representations of these components
    in the OpenBus System world are configured in a similar fashion
    - simply choose the Configure command from the associated right-click menu,
    or double-click on the component directly.

    Configuration of the interconnect and bus mastering devices in an OpenBus System is also streamlined
    with much of the configuration handled behind the scenes.
    For example, there is no manual addition and deletion of devices to
    and from an interconnect. If a link exists between a peripheral and the interconnect,
    the device will automatically be listed in the dialog.

    Fortunately, information is acquired from the peripheral itself, so no having to enter addressing modes,
    data or address bus widths. In fact for most designs, all you'll need to do is specify
    where in a processor's address space a linked peripheral is to be located
    - making design not only fast and efficient, but a pleasure!


    Figure 35. Example of interconnect configuration - simplicity itself!

    Configuring Processor Address Space

    An OpenBus System incorporating a 32-bit processor will typically involve the connection
    of slave memory and peripheral devices
    - to the processor's external memory and peripheral I/O interfaces respectively.

    Unlike a schematic-based design, you are not required to manually define the mapping
    of these devices into the processor's address space as this is handled for you.

    Mapping information is supplied through the respective configuration dialogs
    (processor, peripherals, memories and interconnects).
    OpenBus System simply takes this information and dynamically maps each device memory
    or peripheral device accordingly.

    Interfacing to the Schematic Sheet

    Once your OpenBus System is defined and configured,
    it needs to interface to the top-level schematic in the FPGA design which is handled
    through a sheet symbol placed on the schematic sheet.

    Remember that sheet entries required to populate the sheet symbol are found through
    use of the Schematic Editor's sheet entries and ports synchronization feature launched from
    Sheet Symbol Actions » Synchronize Sheet Entries and Ports.

    The last stage required to hook an OpenBus System into the FPGA design is to wire-up the external interface circuitry.
    This is the circuitry that runs between the external interfaces of the peripherals in the OpenBus System,
    and the physical pins of the FPGA device in which the design will be programmed.
    It includes any additional logic devices used in the design.

     
    Altium Designer:使用 OpenBus System 簡化 FPGA 嵌入式系統設計(PDF檔案下載)
    http://bbs.stella.com.tw/forums/post/1436.aspx


    New - C-to-Hardware Compiler

    Altium Designer 6.8 introduces a powerful C-to-Hardware Compiler (CHC),
    which takes standard untimed ISO-C source code and produces a synthesizable hardware file (RTL).

    Upon synthesis, this RTL description is translated into an electronic circuit that implements the required functions.
    C-to-Hardware Compiler is used in conjunction with Altium Designer's traditional embedded software compilers,
    allowing you to create designs where an embedded processor can offload critical functions to hardware.

    With Altium Designer's C-to-Hardware Compiler, you don't need to know anything about programming in a HDL language,
    such as VHDL or Verilog. Simply write both hardware and software functions in the same C source code file.

    Once your software code is fully debugged, the generated hardware can be produced
    - no more time-consuming simulations for debugging hand-written RTL descriptions,
    leading to reduced development costs and quicker time to market.

    Altium DesignerC to Hardware
    編譯器入門介紹
    http://bbs.stella.com.tw/forums/post/1969.aspx


    Ease of Implementation

    Using the C-to-Hardware Compiler is a straightforward process.
    On the embedded software side simply write your C source code, including the functions intended for hardware.
    On the hardware (FPGA design) side,
    you add an appropriately-configured Application Specific Processor peripheral (ASP).


    Figure 36. Example of an ASP component wired into an OpenBus System described later.
    From a schematic document,
    peripherals are placed as a WB_ASP component from the FPGA Peripherals integrated library.

    From an OpenBus System document, place an ASP component from the Peripherals section of the OpenBus Palette panel.
    Once wired into an FPGA design just like any other peripheral,
    the ASP enables a host processor access and control over hardware-compiled functions within.
    These functions populate the ASP once the design project has been compiled and synthesized.

    For a design that contains common variables accessed by software and hardware functions,
    these variables are allocated in shared memory (for example in FPGA Block RAM or external SRAM),
    with both processor and ASP wired to this memory.
    The ASP has an external memory interface for connection to this memory,
    wired in the same manner as for any other memory-based peripheral.


    Figure 37. The configure dialog is control-central for enabling C-to-Hardware compilation
    - choosing which functions to be implemented in hardware and which variables should be allocated in hardware.


    Use the right hand side of the dialog to determine variables to allocate in hardware
    and functions to be implemented in hardware.
    The upper list reflects all global variables present in the linked embedded software project.
    If you want to have a variable allocated in hardware,
    simply enable the corresponding check box in the Allocate in Hardware column.
    Such a variable will be allocated in ASP block RAM by the CHC Compiler.
    Access to this memory is much faster, in comparison to storage allocation in block RAM outside
    of the ASP by the Embedded Compiler.

    The lower list reflects all functions present in the linked embedded software project.
    If you want to implement a function in hardware - generated by the CHC Compiler as part of the ASP
    - simply enable the corresponding check box in the Implement in Hardware column.

    Should you wish to be able to call that hardware function
    from within the software running on the host processor,
    ensure that the corresponding check box in the Export to Software column is also enabled.
    Allocation of variables and implementation of functions in hardware can also be performed
    from within the C source code
    - either from the C To Hardware panel, or by right-clicking on a global variable/function
    directly in the code editor and using the relevant commands that appear on the context menu.
    When using the panel, only global variables and functions defined in the active C document will be listed.

    To Generate or Not to Generate...

    When configuring the ASP component, two of the most important options you will ever need to
    use are Generate ASP and Use ASP from Software.

    The Generate ASP option provides the ability to enable or disable generation of hardware-compiled functions.
    With this option enabled, the C-to-Hardware Compiler will be invoked
    when you compile and synthesize your design project.
    All functions that have been enabled for implementation in hardware will be created as electronic circuits in the FPGA fabric.

    The Use ASP from Software option enables you to control, on a global level,
    whether functions compiled into hardware will be called by software-based functions running within the processor.
    If this option is disabled, the embedded compiler will generate the functions in software and these will be used.

    If a design has been processed with the Generate ASP option enabled,
    then if the state of the Use ASP from Software option is changed,
    you only need to recompile and download the updated embedded software.

    Full reprocessing of the entire FPGA project is not required as the logic for the hardware functions already exists.
    In this way you can quickly switch between software-only and software-hardware implementations of the design,
    to observe the benefits obtained by using hardware acceleration.

     
    Altium DesignerGetting Started with the C-to-Hardware Compiler (PDF檔案)
    http://bbs.stella.com.tw/forums/post/3776.aspx
    Altium Designer:C-to-Hardware Compiler User Manual (PDF檔案)
    http://bbs.stella.com.tw/forums/thread/3898.aspx


    For information on the ASP component, refer to the document
    [WB_ASP Configurable Wishbone Application Specific Processor]

    Improved - Version Control

    Version control has been improved to provide better feedback and more intuitive usage
    - files status can be refreshed from both the Storage Manager panel (right-click and select Refresh or hit F5).
    Additionally, file status is more informative, making it easier to see which files need to be committed or updated.

    Figure 38. You can also manage conflicts and missing files from here.
    Any revisions that you have currently checked out display a blue arrow ( ) in the VCS Revisions section.

    Two new version control statuses are reported:
    Missing means that the file is present in the repository but not on your local hard drive.
    This can happen if a file is deleted or renamed, or if a new file is added to the project.
    Missing files can be retrieved from the repository by selecting Restore on the right-click menu.

    Conflict means that someone has committed changes to the file before you have had a chance to commit your own.
    Files that are in conflict cannot be committed until the conflict is resolved.

    New - Actel ® Fusion support


    Altium Designer now has full support for the Actel Fusion family of FPGA devices,
    including PCB/FPGA integration, Board Level and FPGA libraries, Synthesis, Programming and LiveDesign.

    Embedded Flash Blocks are used to initialize the internal memory of 32-bit processors
    making the Fusion devices a perfect platform for Embedded applications.
    All analog functionality is accessible and configurable through
    a new Analog Block System configurable component (AB_SYSTEM).


    Figure 39. Altium Designer includes a new configurable component to take advantage of the Analog
    to Digital converter integrated inside the FPGA.
    This component lets you configure the resolution, sampling, analog input and gate driver.

    Improved - NXP LPC2000 ® Series Support

    Support for the NXP LPC2000 ® Series of discrete ARM7-based processor devices has been improved.
    You can now download code to the on-board Flash memory of these devices via Altium Designer.
    Support for hardware breakpoints facilitates subsequent debugging of this code.

    In addition, Altium Designer is aware of the internal memory structures of all devices in this range of processors.
    Embedded projects using these devices will automatically be configured with the correct memory layout information.

    New - FPGA Peripheral Cores

    Expanding your options for peripherals, Altium Designer 6.8 adds support for a number of new peripheral cores.
    For schematic-based design of your main processor system, all peripherals can be found in, and placed from,
    the FPGA Peripherals integrated library (\Program Files\Altium Designer\Library\Fpga\FPGA Peripherals.IntLib.
    For a design incorporating an OpenBus System, all components can be found in,
    and placed from, the OpenBus Palette panel.

    WB_ASP

    The WB_ASP peripheral is an Application Specific Processor used as a container for C source functions
    that are implemented in hardware through use of the C-to-Hardware Compiler described earlier in this document.

    WB_IDE

    The WB_IDE is a Wishbone-compliant peripheral that provides the control interface
    between an IDE-compatible storage device, such as a hard disk or Compact Flash memory card,
    and a processor in the FPGA design.

    WB_IRCODER

    The WB_IRCODER peripheral provides the interface between an infrared transmitter and a processor in an FPGA design.
    The peripheral has been built primarily to interface to the TFDU6102 Fast Infrared Transceiver
    (from Vishay Semiconductor) found on Altium's USB-IrDA-Ethernet Peripheral Board PB03.

    However, it could be used to interface to any IR transmitter where the required input signal is already modulated
    and simply controls the pulsing of the transmitter's IRLED.

    The peripheral encodes remote control codes using the NEC IR transmission protocol
    and handles the modulation of the signal at the carrier frequency associated with this protocol - 38kHz.

    WB_IRDEC

    The WB_IRDEC peripheral provides the interface between an infrared receiver and a processor in an FPGA design.
    The peripheral has been built primarily to interface to the TFDU6102 Fast Infrared Transceiver
    (from Vishay Semiconductor) found on Altium's USB-IrDA-Ethernet Peripheral Board PB03.

    However, it could be used to interface to any photodiode circuit
    or IR receiver where the output signal is passed on, still in modulated form.

    The peripheral handles demodulation of the incoming signal and can be configured to operate in one of two modes
    - either as a dedicated decoder for data transmitted using the NEC IR transmission protocol,
    or as a raw interface, allowing the reception of data encoded in any other format.
    In the latter mode the encoded data is received by the processor, to be decoded in software.

    WB_JPGDEC

    The WB_JPGDEC peripheral facilitates the decoding of baseline JPEG-compressed images (grayscale and color)
    into RGB565 pixel format output that can be written directly to screen display memory,
    or to a continuous external memory storage area.

    The full JPEG image can be decoded, or only a specified area.
    The peripheral also supports block-based reading and writing.

    WB_OWM

    The WB_OWM is a 1-Wire® Master Controller that facilitates communications between
    an FPGA-based processor and external 1-Wire-compatible peripheral devices, over the 1-Wire serial bus.

    The Controller handles all timing and control signals required to satisfy the 1-Wire protocol.
    Once mapped into the processor's peripheral I/O space it is seen and used by the processor as a dedicated 1-Wire port.
    The processor simply has to set up interrupts, issue control commands, and send and receive data.

    WB_SHARED_MEM_CTRL

    The WB_SHARED_MEM_CTRL is a Wishbone-compliant configurable memory controller that,
    depending on its configuration, provides an interface between a 32-bit processor and memories on a shared bus.
    The Controller provides access to, and use of, the following three different types of memory,
    each of which is multiplexed for access over shared data and address busses:

    • Asynchronous Static RAM
    • Single data rate Synchronous DRAM
    • Parallel Flash memory
      The Controller handles all multiplexing for you, negating the need for custom demultiplexing logic.
      Note: The WB_SHARED_MEM_CTRL is primarily designed to be used with
      the common-bus memories located on Altium's 3-connector daughter boards,
      such as the Xilinx Spartan-3 Daughter Board DB30. Provided the same pinout is used,
      the Controller could be used to interface to other memories of the types supported,
      and which are accessed using shared bus architecture.

    New - Lattice SC ® support


    Support for the Lattice SC ® range of devices has been added:

    • SC15 (LFSC3GA15E)
    • SC25 (LFSC3GA25E)
    • SC80 (LFSC3GA80E)
      You can now use the Altium Designer environment to work with these powerful and flexible Lattice devices.
      More information on the supported devices can be found through the Browse Physical Devices dialog.
      Access this dialog from the Devices view (View » Devices View)
      by choosing the Browse Physical Devices entry in the main Tools menu.

    New - Actel CoreMP7 Support

    Altium Designer 6.8 supports use of the following CoreMP7 processor with the following Actel base FPGA devices:
    *Fusion
    **M7AFS600
    *ProASIC3
    **M7A3P250
    **M7A3P400
    **M7A3P600
    **M7A3P1000

    Altium Designer now includes Wishbone wrapper support for Actel's 'soft' CoreMP7 RISC processor core,
    for use in FPGA designs targeting supported Actel Fusion or ProASIC®3 families of physical FPGA devices.

    Similar to (and fully compatible with) the ARM7TDMI-S™ core processor,
    the CoreMP7 is an implementation of the ARM® architecture v4T.
    Only designs targeting the supported Fusion or ProASIC3 FPGA devices,
    listed to the right, may make use of the processor.


    Improved - Flash Memory Support


    The existing configurable Memory Controller component (WB_MEM_CTRL) has been improved to
    now support connection to Parallel Flash memory.
    This is similar to the Parallel Flash memory support offered by the new Shared Memory Controller device
    (refer back to New - FPGA Peripheral Cores).

    Whereas the Shared Memory Controller supports interface to the single 16-bit (32MB) Flash memory
    found on the upcoming 3-connector daughter boards associated with the Desktop NanoBoard NB2DSK01,
    the WB_MEM_CTRL device offers interface support to a wider range of Flash memory sizes and layouts.

    New - LiveDesign Instrument


    Greatly improving FPGA debugging capabilities, three new LiveDesign instruments
    give you yet more options for testing your designs.
    These appear in the Devices view in the software chain after compiling and synthesizing your FPGA project.

    Terminal Console


    Console IO is a common way of debugging processor systems,
    and with this release you will be able to type text directly in the Terminal console to send text to your device.

    The Terminal is Wishbone-compatible and is connected to the design the same way
    as any other WB-compatible peripheral.
    Reading/writing to this instrument from embedded code is very similar to reading/writing to the WB_UART8 peripheral.

    Configurable Digital I/O

    If you have already used one of the IOB instruments, you'll find this new instrument works in a similar fashion.
    With Configurable Digital I/O highly customizable interface,
    you can change the display format of input and output using graphical widgets that can be configured
    for your design as well as the ability to configure input and output busses, and initial output values.

    Altium Designer:IOB_x Digital I/O Module (PDF檔案)
    http://bbs.stella.com.tw/forums/post/3800.aspx
    Altium Designer:如何使用虛擬的數位 IO  (Digital IO) (線上動畫)
    http://bbs.stella.com.tw/forums/thread/2171.aspx
    Altium Designer
    :如何設置 FPGA 數位IO模組 (Setup FPGA IO ) (線上動畫)
    http://bbs.stella.com.tw/forums/thread/2100.aspx
    Altium Designer
    FPGA IO Standards Reference (PDF檔案)
    http://bbs.stella.com.tw/forums/thread/3789.aspx



    CrossPoint Switch

    Debugging FPGAs can be made easier by having multiplexers with their switching inputs driven
    by a digital IO instrument.
    The Crosspoint Switch instrument is designed for just this purpose!
    This nifty instrument allows you to define which inputs go to which outputs.
    You can even opt to disconnect inputs and outputs.

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